Integrated circuits are typically manufactured using “layouts”, which are collections of polygons and/or other shapes in two-dimensions. These polygons might be physically incorporated into “masks”, with one or more masks being used to define the locations of each fabrication layer, e.g., diffusion, contacts, polysilicon (also known as “poly”), vias, metal 1, metal 2, and so forth. Alternatively or additionally, the polygons might form a database that is used to directly control the application of a layer to the surface of the wafer, without the use of a physical mask. In either case, the polygons define the areas of the polysilicon to which a new layer will be applied or from which an existing layer will be removed during the semiconductor fabrication process.
Although IC circuits are typically simulated prior to layout, it is desirable to simulate a circuit after layout as well, a process known as “post-layout simulation”. Post-layout simulation provides a more accurate depiction of the circuit behavior than a simulation of the circuit prior to layout, and may detect, for example, discrepancies between the layout and the original circuit design. To perform a post-layout simulation, a netlist is extracted from the layout and the simulation is performed upon this netlist. The extracted netlist may include, for example, a specification of transistors implemented by the layout, interconnections between the transistors, width and length values for each transistor, parasitics for each transistor, and parasitic capacitances and resistances for the interconnections between the transistors.
However, the semiconductor fabrication process typically alters some characteristics of an IC layout, such as the length and/or width of transistors, and these effects become more pronounced for nanometer processes at smaller dimensions. It is common practice to account for this discrepancy during post-layout simulation by using complicated simulation models designed to predict the behavior of post-fabrication transistors. While these transistor models can be quite accurate, their development is time-consuming, and changes to the fabrication process typically require what may be extensive modification of each transistor model. Further, the use of these models complicates the simulation process to the point where post-layout simulation requires extensive amounts of time and computing power.
Therefore, it is desirable to find alternative computer-implemented methods of performing post-layout simulation that reduce the amount of time and computing-power required to perform post-layout simulation, while retaining a sufficient level of accuracy to provide confidence in the result.